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1 for more information www.linear.com/ltc7813 typical a pplica t ion fea t ures descrip t ion low i q , 60v synchronous boost+buck controller the lt c ? 7813 is a high performance synchronous boost+buck dc/dc switching regulator controller that drives all n-channel power mosfet stages. it contains independent step-up ( boost) and step-down ( buck) controllers that can regulate two separate outputs or be cascaded to regulate an output voltage from an input voltage that can be above, below, or equal to the output voltage. the ltc7813 operates from a wide 4.5v to 60v input supply range. when biased from the output of the boost regulator, the ltc7813 can operate from an input supply as low as 2.2v after start-up. the 34a no-load quiescent current (both channels on) extends operating runtime in battery-powered systems. unlike conventional buck-boost regulators, the ltc7813 s cascaded boost+ buck solution has continuous, non- pulsating, input and output currents, substantially reducing voltage ripple and emi. the ltc7813 has independent feedback and compensation points for the boost and buck regulation loops, enabling a fast output transient response that can be externally optimized. a pplica t ions n synchronous boost and buck controllers n when cascaded, allows v in above, below, or equal to regulated v out of up to 60v n wide bias input voltage range: 4.5v to 60v n output remains in regulation through input dips (e.g. cold crank) down to 2.2v n adjustable gate drive level 5v to 10v (opti-drive) n low emi with low input and output ripple n fast output transient response n no external bootstrap diodes required n high light load effciency n low operating i q : 29a (one channel on) n low operating i q : 34a (both channels on) n r sense or lossless dcr current sensing n buck output voltage range: 0.8v v out 60v n boost output voltage up 60v n phase-lockable frequency (75khz to 850khz) n small 32-pin 5mm 5mm qfn package n automotive and industrial power systems n high power battery operated systems l, lt , lt c , lt m , linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. wide input range to 10v/10a low i q cascaded boost+buck regulator ltc 7813 7813f 1f 0.1f 6.8f 4 47f 47f 47f 0.1f 0.1f 22f 3 22f 3 2.2h 33pf 100pf 3300pf 8.87k v in 470pf 22nf 6.19k 0.1f 0.1f 10h 4.7f 37.4k sense2+ sense2? bg2 sw2 boost2 tg2 intv cc gnd 1.62k v fb2 v bias tg1 boost1 sw1 bg1 sense1+ sense1? v fb1 extv cc 15k v out 10v 10a* v in 8v to 60v down to 2.2v after start-up run1 run2 2.32k i th1 i th2 track/ss1 ss2 freq pllin/mode ilim drvuv drvset drv cc r b1 332k v mid , 12v** * when v in <8v maximum load current available is reduced **v mid = 12v when v in < 12v v mid follows v in when vin > 12v ltc7813 vprg2 7813 ta01 r a1 11.5k 0.1f
2 for more information www.linear.com/ltc7813 p in c on f igura t ion a bsolu t e maxi m u m r a t ings bias input supply voltage (v bias ) .............. C0.3 v to 65 v topside driver voltages boos t 1, boost2 .................................. C 0.3 v to 76 v switch voltage (sw 1, sw 2) .......................... C5 v to 70 v drv cc , (boost 1- sw 1), ( boost 2- sw 2) .... C 0.3 v to 11 v bg 1, bg 2, tg 1, tg 2 ........................................... ( no te 8) run 1, run 2 voltages ................................ C 0.3 v to 65 v sense 1 + , sense 2 + , sense 1 C sense 2 C voltages ..................................... C 0.3 v to 65 v pllin / mode , freq , drvset voltages ....... C 0.3 v to 6v extv cc voltage ......................................... C 0.3 v to 14 v ith 1, ith 2, v fb 1 voltages ............................ C 0.3 v to 6v v fb 2 voltage ............................................... C 0.3 v to 65 v vprg 2 voltage ............................................ C0. 3 v to 6v track / ss 1, ss 2 voltages ........................... C 0.3 v to 6v operating junction temperature range ( notes 2, 3) ltc 7 813 e , ltc 7813 i .......................... C 40 c to 125 c ltc 7 813 h .......................................... C 40 c to 150 c ltc 7 813 mp ....................................... C 55 c to 150 c storage temperature range .................. C 65 c to 150 c (note 1) 32 33 gnd 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1sw1 tg1 track/ss1 vprg2 i th1 v fb1 sense1 + sense1 ? drv cc ss2 drvset drvuv i th2 v fb2 ilim run2 boost1 bg1 sw2 tg2 boost2 bg2 v bias extv cc freq pllin/mode gnd sense2 + sense2 ? pgood1 intv cc run1 t jmax = 150c, ja = 44c/w exposed pad (pin 33) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc7813euh#pbf ltc7813euh#trpbf 7813 32-lead (5mm 5mm) plastic qfn C40c to 125c ltc7813iuh#pbf ltc7813iuh#trpbf 7813 32-lead (5mm 5mm) plastic qfn C40c to 125c ltc7813huh#pbf ltc7813huh#trpbf 7813 32-lead (5mm 5mm) plastic qfn C40c to 150c ltc7813mpuh#pbf ltc7813mpuh#trpbf 7813 32-lead (5mm 5mm) plastic qfn C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc 7813 7813f
3 for more information www.linear.com/ltc7813 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v bias = 12v, v run1,2 = 5v, v extvcc = 0v, v drvset = 0v, vprg2 = 0v unless otherwise noted. symbol parameter conditions min typ max units v bias bias input supply operating voltage range 4.5 60 v v out1 buck regulated output voltage set point 0.8 60 v v out2 boost regulated output voltage set point 60 v v sense2(cm) sense2 pins common mode range (boost converter input supply voltage) 2.2 60 v v fb1 buck regulated feedback voltage (note 4) ith1 voltage = 1.2v 0c to 85c l 0.792 0.788 0.800 0.800 0.808 0.812 v v v fb2 boost regulated feedback voltage (note 4) ith2 voltage = 1.2v vprg2 = 0v vprg2 = float vprg2 = intv cc l l l 1.182 9.78 11.74 1.200 10.00 12.00 1.218 10.22 12.26 v v v i fb1 buck feedback current (note 4) C2 50 na i fb2 boost feedback current (note 4) vprg2 = 0v vprg2 = float vprg2 = intv cc 0.01 4 5 0.05 6 7 a a a reference v oltage line regulation (note 4) v bias = 4.5v to 60v 0.002 0.02 %/v output voltage load regulation (note 4) measured in servo loop, ? ith voltage = 1.2v to 0.7v l 0.01 0.1 % (note 4) measured in servo loop, ? ith voltage = 1.2v to 2v l C0.01 C0.1 % g m1,2 transconductance amplifier g m (note 4) ith1,2 = 1.2v, sink/source 5a 2 mmho i q input dc supply current (note 5), v drvset = 0v pulse-skipping or forced continuous mode (one channel on) run1 = 5v and run2 = 0v or run2 = 5v and run1 = 0v v fb1 = 0.83v (no load), v fb2 = 1.25v (no load) 1.6 0.8 ma ma pulse-skipping or for ced continuous mode (both channels on) run1,2 = 5v, v fb1 = 0.83v (no load), v fb2 = 1.25v (no load) 2.2 ma sleep mode (one channel on, buck) run 1 = 5v and run2 = 0v v fb1 = 0.83v (no load) l 29 55 a sleep mode (one channel on, boost) run2 = 5v and run1 = 0v, v fb2 = 1.25v (no load) 29 50 a sleep mode (both channels on) run1 = 5v and run2 = 5v, v fb1 = 0.83v (no load), v fb2 = 1.25v (no load) 34 55 a shutdown run1, 2 = 0v 3.6 10 a uvlo undervoltage lockout drv cc ramping up drvuv = 0v drvuv = intv cc l l 4.0 7.5 4.2 7.8 v v d rv cc ramping down drvuv = 0v drvuv = intv cc l l 3.6 6.4 3.8 6.7 4.0 7.0 v v buck feedback over voltage protection measured at v fb1 relative to regulated v fb1 7 10 13 % sense1 + pin current 1 a sense2 + pin current 170 a sense1 C pin current v sense1 C < v intvcc C 0.5v v sense1 C > v intvcc + 0.5v 700 1 a a sense2 C pin current v sense2 +, v sense2 C = 12v 1 a ltc 7813 7813f
4 for more information www.linear.com/ltc7813 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v bias = 12v, v run1,2 = 5v, v extvcc = 0v, v drvset = 0v, vprg2 = 0v unless otherwise noted. symbol parameter conditions min typ max units maximum duty factor for tg buck (channel 1) in dropout, freq = 0v boost (channel 2) 97.5 99 100 % % maximum duty factor for bg buck (channel 1) in over voltage boost (channel 2) 100 96 % % i track/ss1 soft-start charge current v track/ss1 = 0v 8 10 12 a i ss2 soft-start charge current v ss2 = 0v 8 10 12 a v run1,2 on run pin on threshold v run1 , v run2 rising l 1.22 1.275 1.33 v run pin hysteresis 75 mv v sense1,2(max) maximum current sense threshold i lim = float i lim = 0v i lim = intv cc l l l 65 43 90 75 50 100 85 58 109 mv mv mv gate driver tg 1, 2 pull-up on-resistance pull-down on-resistance v drvset = intv cc 2.2 1.0 bg 1, 2 pull-up on-resistance pull-down on-resistance v drvset = intv cc 2.2 1.0 boost 1, 2 to drv cc switch on-resistance v sw1,2 = 0v, v drvset = intv cc 3.7 tg transition time: rise time fall time (note 6) v drvset = intv cc c load = 3300pf c load = 3300pf 25 15 ns ns bg transition t ime: rise time fall time (note 6) v drvset = intv cc c load = 3300pf c load = 3300pf 25 15 ns ns top gate off to bottom gate on delay synchronous switch-on delay t ime c load = 3300pf each driver, v drvset = intv cc buck (channel 1) boost (channel 2) 55 85 ns ns bottom gate off to top gate on delay t op switch-on delay time c load = 3300pf each driver, v drvset = intv cc buck (channel 1) boost (channel 2) 50 80 ns ns t on(min)1 buck minimum on-time (note 7) v drvset = intv cc 80 ns t on(min)2 boost minimum on-time (note 7) v drvset = intv cc 120 ns drv cc linear regulator drv cc voltage from internal v bias ldo v extvcc = 0v 7v < v bias < 60v, drvset = 0v 11v < v bias < 60v, drvset = intv cc 5.8 9.6 6.0 10.0 6.2 10.4 v v d rv cc load regulation from v bias ldo i cc = 0ma to 50ma, v extvcc = 0v 0.9 2.0 % drv cc voltage from internal extv cc ldo 7v < v extvcc < 13v, drvset = 0v 11v < v extvcc < 13v, drvset = intv cc 5.8 9.6 6.0 10.0 6.2 10.4 v v d rv cc load regulation from internal extv cc ldo i cc = 0ma to 50ma, v extvcc = 8.5v, v drvset = 0v 0.7 2.0 % extv cc ldo switchover voltage extv cc ramping positive drvset = 0v or r drvset 100k drvset = intv cc 4.5 7.4 4.7 7.7 4.9 8.0 v v ext v cc hysteresis 250 mv programmable drv cc r drvset = 50k, v extvcc = 0v 5.0 v programmable drv cc r drvset = 70k, v extvcc = 0v 6.4 7.0 7.6 v programmable drv cc r drvset = 90k, v extvcc = 0v 9.0 v ltc 7813 7813f
5 for more information www.linear.com/ltc7813 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v bias = 12v, v run1,2 = 5v, v extvcc = 0v, v drvset = 0v, vprg2 = 0v unless otherwise noted. symbol parameter conditions min typ max units oscillator and phase-locked loop programmable frequency r freq =25k, pllin/mode = dc voltage 105 khz programmable frequency r freq = 65k, pllin/mode = dc voltage 375 440 505 khz programmable frequency r freq = 105k, pllin/mode = dc voltage 835 khz low fixed frequency v freq = 0v, pllin/mode = dc voltage 320 350 380 khz high fixed frequency v freq = intv cc , pllin/mode = dc voltage 485 535 585 khz synchronizable frequency pllin/mode = external clock l 75 850 khz pllin v ih pllin v il pllin/mode input high level pllin/mode input low level pllin /mode = external clock pllin/mode = external clock l l 2.5 0.5 v v boost 2 charge pump boost2 charge pump available output current freq = 0v, pllin/mode = int v cc v boost2 = 16.5v, v sw2 = 12v v boost2 = 19v, v sw2 = 12v 75 35 a a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum ratings for extended periods may affect device reliability and lifetime. note 2: the ltc7813 is tested under pulsed load conditions such that t j t a . the ltc7813e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc7813i is guaranteed over the C40c to 125c operating junction temperature range, the ltc7813h is guaranteed over the C40c to 150c operating junction temperature range and the ltc7813mp is tested and guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja = 44c. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: the ltc7813 is tested in a feedback loop that servos v ith1,2 to a specified voltage and measures the resultant v fb1,2 . the specification at 85c is not tested in production and is assured by design, characterization and correlation to production testing at other temperatures (125c for the ltc7813e and ltc7813i, 150c for the ltc7813h and ltc7813mp). for the ltc 7813i and ltc7813h, the specification at 0c is not tested in production and is assured by design , characterization and correlation to production testing at C40c. for the ltc7813mp, the specification at 0c is not tested in production and is assured by design, characterization and correlation to production testing at C55c. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels note 7: the minimum on-time condition is specified for an inductor peak-to-peak ripple current >40% of i max (see minimum on-time considerations in the applications information section). note 8: do not apply a voltage or current source to these pins. they must be connected to capacitive loads only, otherwise permanent damage may occur. ltc 7813 7813f
6 for more information www.linear.com/ltc7813 typical p er f or m ance c harac t eris t ics power loss vs load current, v in = 18v power loss vs load current, v in = 24v power loss vs load current, v in = 36v efficiency vs input voltage buck regulated feedback voltage vs temperature boost regulated feedback voltage vs temperature efficiency vs load current, v in = 18v efficiency vs load current, v in = 24v efficiency vs load current, v in = 36v temperature (c) -75 regulated feedback voltage (mv) 808 806 802 804 800 796 798 794 792 -25 25 -50 0 75 100 7813 g08 150 50 125 temperature (c) -75 regulated feedback voltage (v) 1.212 1.209 1.203 1.206 1.2 1.194 1.197 1.191 1.188 -25 25 -50 0 75 100 7813 g09 150 50 125 ltc 7813 7813f 1 0.0001 0.001 0.01 0.1 1 7 0.001 0.01 0.1 1 7 10 power loss (w) 7813 g05 figure 15 circuit v out = 24v burst mode ps mode fc mode load current (a) 0.0001 0 0.001 0.01 0.1 1 7 0.001 0.01 0.1 1 10 10 power loss (w) 7813 g06 figure 15 circuit v out = 24v burst mode ps mode fc mode figure 15 circuit v out = 24v i out = 2a 20 i out = 4a input voltage (v) 5 10 15 20 25 30 35 40 30 45 50 55 60 90 92 94 96 98 100 40 efficiency (%) 7813 g07 50 60 70 burst mode 80 90 100 efficiency (%) figure 15 circuit v out = 24v 7813 g01 ps = pulse-skipping fc = forced continuous load current (a) 0.0001 ps mode 0.001 0.01 0.1 1 7 0 10 20 30 40 fc mode 50 60 70 80 90 100 efficiency (%) 7813 g02 figure 15 circuit v out = 24v load current (a) burst mode ps mode fc mode load current (a) 0.0001 0.001 0.01 0.1 1 7 0.0001 0 10 20 30 40 50 60 70 80 90 0.001 100 efficiency (%) 7813 g03 figure 15 circuit v out = 24v burst mode ps mode fc mode load current (a) 0.0001 0.01 0.001 0.01 0.1 1 7 0.001 0.01 0.1 1 10 0.1 power loss (w) 7813 g04 figure 15 circuit v out = 24v burst mode ps mode fc mode bm ps load current (a)
7 for more information www.linear.com/ltc7813 typical p er f or m ance c harac t eris t ics load step at v in = 18v, pulse-skipping mode load step at v in = 24v, pulse-skipping mode load step at v in = 36v, pulse-skipping mode load step at v in = 24v, forced continuous mode load step at v in = 36v, forced continuous mode load step at v in = 18v, burst mode operation load step at v in = 24v, burst mode operation load step at v in = 36v, burst mode operation load step at v in = 18v, forced continuous mode 200s/div figure 15 circuit v out = 24v v out 500mv/div ac-coupled i l1 1a/div 7813 g10 200s/div v out 500mv/div ac-coupled i l1 1a/div 7813 g11 figure 15 circuit v out = 24v 200s/div v out 500mv/div ac-coupled i l1 1a/div 7813 g12 figure 15 circuit v out = 24v 200s/div v out 500mv/div ac-coupled i l1 1a/div 7813 g13 figure 15 circuit v out = 24v 200s/div v out 500mv/div ac-coupled i l1 1a/div 7813 g14 figure 15 circuit v out = 24v 200s/div v out 500mv/div ac-coupled i l1 1a/div 7813 g16 figure 15 circuit v out = 24v 200s/div v out 500mv/div ac-coupled i l1 1a/div 7813 g17 figure 15 circuit v out = 24v 200s/div v out 500mv/div ac-coupled i l1 1a/div 7813 g18 figure 15 circuit v out = 24v 200s/div v out 500mv/div ac-coupled i l1 1a/div 7813 g15 figure 15 circuit v out = 24v ltc 7813 7813f
8 for more information www.linear.com/ltc7813 typical p er f or m ance c harac t eris t ics sense pins input current vs v sense voltage buck sense1 C pin input bias current vs temperature boost sense2 pins input current vs temperature maximum current sense threshold vs duty cycle maximum current sense threshold vs i th voltage track/ss1 and ss2 pull-up current vs temperature drv cc line regulation drv cc and extv cc vs load current extv cc switchover and drv cc voltages vs temperature input voltage (v) 0 5 drv cc voltage (v) 11 9 7 10 8 6 5 65 25 45 55 15 35 60 20 40 50 10 30 7813 g19 drvset = intv cc drvset = gnd load current (ma) 0 drv cc voltage (v) 6.4 5.6 4.8 6 5.2 4.4 6.2 5.4 4.6 5.8 5 4.2 4 150 75 25 125 50 100 7813 g20 extv cc = 0v extv cc = 8.5v v bias = 12v drvset = gnd extv cc = 5v temperature (c) -75 drv cc voltage (v) 11 10 8 9 7 5 6 4 -25 25 -50 0 75 100 7813 g21 150 50 125 extv cc rising extv cc falling extv cc rising extv cc falling drv cc drv cc drvset = gnd drvset = intv cc v sense common mode voltage (v) 0 5 sense current (a) 800 500 200 700 400 600 300 100 0 65 25 45 55 15 35 60 20 40 50 10 30 7813 g22 sense1 ? pin (buck) sense2 + pin (boost) temperature (c) -75 sense1 ? current (a) 900 800 600 700 500 200 400 100 300 0 -25 25 -50 0 75 100 7813 g23 150 50 125 v out1 > intv cc + 0.5v v out1 < intv cc ? 0.5v temperature (c) -75 sense current (a) 200 180 140 160 120 60 100 40 20 80 0 -25 25 -50 0 75 100 7813 g24 150 50 125 v in = 12v sense2 ? pin sense2 + pin duty cycle (%) 0 maximum current sense voltage (a) 100 90 70 80 60 30 50 20 10 40 0 20 40 10 30 60 70 7813 g25 100 50 9080 buck boost temperature (c) -75 track/ss and ss2 current (a) 12 11.5 11 9.5 10.5 9 8.5 10 8 -25 25 -50 0 75 100 7813 g27 150 50 125 v ith (v) 0 current sense voltage (mv) 100 0 ?20 ?40 80 40 60 20 7813 g26 1.4 0.2 0.6 1.210.8 0.4 i lim = gnd i lim = float i lim = intv cc burst mode operation 5% duty cycle pulse-skipping forced continuous mode ltc 7813 7813f
9 for more information www.linear.com/ltc7813 typical p er f or m ance c harac t eris t ics buck foldback current limit oscillator frequency vs temperature undervoltage lockout threshold vs temperature boost2 charge pump charging current vs frequency boost2 charge pump charging current vs switch voltage shutdown current vs temperature shutdown current vs input voltage boost2 charge pump output voltage vs sw2 voltage quiescent current vs temperature temperature (c) -75 shutdown current (a) 8 7 6 3 5 2 1 4 0 -25 25 -50 0 75 100 7813 g28 150 50 125 v bias = 12v v bias input voltage (v) 0 shutdown current (a) 14 12 6 10 4 2 8 0 20 40 10 30 60 7813 g29 65 50 5 25 45 15 35 55 temperature (c) -75 frequency (khz) 600 500 550 450 350 400 300 -25 25 -50 0 75 100 7813 g32 150 50 125 freq = intv cc freq = gnd temperature (c) -75 drv cc voltage (v) 8 5 5.5 4.5 3.5 4 7 7.5 6.5 6 3 -25 25 -50 0 75 100 7813 g33 150 50 125 rising rising falling falling drvuv = intv cc drvuv = gnd sw2 voltage (v) 5 boost2 ? sw2 voltage (v) 10 2 8 6 4 9 7 5 3 0 1 65 25 45 55 15 35 60 20 40 50 10 30 150c 25c ?55c freq = 350khz 10m load between boost2 and sw2 7813 g34 operating frequency (khz) 100 charge pump charging current (a) 100 90 70 80 60 30 50 20 10 40 0 200 400300 600 700 7813 g35 800 500 v boost2 = 16.5v v sw2 = 12v ? 55c 150c 25c sw2 voltage (v) 0 5 charge pump charging current (a) 120 90 100 110 80 50 20 70 40 60 30 10 0 65 25 45 55 15 35 60 20 40 50 10 30 7813 g36 v boost2 ? v sw2 = 4.5v ? 55c ?55c 150c 25c 150c v boost2 ? v sw2 = 7.0v 25c freq = 350khz v fb1 feedback voltage (mv) 0 maximum current sense voltage (mv) 100 90 50 30 70 10 0 80 40 60 20 7813 g31 800 400300 100 600 700 200 500 i lim = intv cc i lim = float i lim = gnd ltc 7813 7813f 75 100 125 150 0 10 20 30 40 50 60 70 80 quiescent current (a) 7813 g30 v bias = 12v one channel on burst mode operation drvset = 70k drvset = intv cc drvset = gnd temperature (c) ?75 ?50 ?25 0 25 50
10 for more information www.linear.com/ltc7813 p in func t ions sw1, sw 2 (pins 1, 30): switch node connections to inductors. tg1, tg 2 (pins 2, 29): high current gate drives for top n-channel mosfets . these are the outputs of floating drivers with a voltage swing equal to drv cc superimposed on the switch node voltage sw. track/ss1, ss 2 (pins 3, 23): external tracking and soft- start input. for the buck channel, the ltc7813 regulates the v fb1 voltage to the smaller of 0.8v, or the voltage on the track/ss1 pin. for the boost channel, the ltc7813 regulates the v fb2 voltage to the smaller of 1.2v, or the voltage on the ss2 pin. an internal 10a pull-up current source is connected to this pin . a capacitor to ground at this pin sets the ramp time to final regulated output voltage. alternatively, a resistor divider on another voltage supply connected to the track/ss1 pin allows the ltc7813 buck output to track the other supply during start-up. vprg2 (pin 4): channel 2 output control pin. this pin sets the boost channel to adjustable output mode using external feedback resistors or fixed 10v/12v output mode using internal resistive dividers. grounding this pin allows the output to be programmed through the v fb2 pin using external resistors, regulating v fb2 to the 1.2v reference. floating this pin or connecting it to intv cc programs the output to 10v or 12v (respectively), with v fb2 used to sense the output voltage. ith1, ith 2 (pins 5, 20): error amplifier outputs and switching regulator compensation points. each associ- ated channels current comparator trip point increases with this control voltage . v fb1 ( pin 6): this pin receives the remotely sensed feedback voltage for the buck controller from an external resistive divider across the output. sense1 + , sense2 + (pins 7, 12): the (+) input to the differential current comparators. the ith pin voltage and controlled offsets between the sense C and sense + pins in conjunction with r sense set the current trip threshold. for the boost channel, the sense2 + pin supplies current to the current comparator. sense1 C , sense2 C (pins 8, 13): the (C) input to the differential current comparators. when sense1 C for the buck channel is greater than intv cc , the sense1 C pin supplies current to the current comparator. freq (pin 9): the frequency control pin for the internal vco. connecting this pin to gnd forces the vco to a fixed low frequency of 350khz. connecting this pin to intv cc forces the vco to a fixed high frequency of 535khz. other frequencies between 50khz and 900khz can be programmed using a resistor between freq and gnd. the resistor and an internal 20 a source current create a voltage used by the internal oscillator to set the frequency. typical p er f or m ance c harac t eris t ics start-up buck inductor current at light load boost inductor current at light load 5ms/div v out 5v/div run 5v/div 7813 g37 figure 15 circuit 5s/div figure 15 circuit v in = 32v v out = 24v i out = 1ma i l1 2a/div 7813 g38 forced continuous mode burst mode operation pulse-skipping mode 5s/div figure 15 circuit v in = 18v v out = 24v i out = 1ma i l2 2a/div 7813 g39 forced continuous mode burst mode operation pulse-skipping mode ltc 7813 7813f
11 for more information www.linear.com/ltc7813 p in func t ions pllin/mode (pin 10): external synchronization input to phase detector and forced continuous mode input . when an external clock is applied to this pin, the phase- locked loop will force the rising tg 1 and bg2 signals to be synchronized with the rising edge of the external clock, and the regulators will operate in forced continuous mode. when not synchronizing to an external clock, this input, which acts on both controllers, determines how the ltc7813 operates at light loads. pulling this pin to ground selects burst mode ? operation. an internal 100k resistor to ground also invokes burst mode operation when the pin is floated . tying this pin to intv cc forces continuous inductor current operation. tying this pin to a voltage greater than 1.1 v and less than intv cc C 1.3 v selects pulse-skipping operation. this can be done by connecting a 100k resistor from this pin to intv cc . gnd (pin 11, exposed pad pin 33): ground. the exposed pad must be soldered to the pcb for rated electrical and thermal performance. pgood1 (pin 14): open-drain logic output. pgood1 is pulled to ground when the voltage on the v fb1 pin is not within 10% of its set point. intv cc (pin 15): output of the internal 5v low dropout regulator. the low voltage analog and digital circuits are powered from this voltage source . a low esr 0.1f ceramic bypass capacitor should be connected between intv cc and gnd, as close as possible to the ic. run1, run 2 (pins 16, 17): run control inputs for each controller. forcing either of these pins below 1.2v shuts down that controller. forcing both of these pins below 0.7v shuts down the entire ltc7813, reducing quiescent current to approximately 3.6a. ilim (pin 18): current comparator sense voltage range input. tying this pin to gnd or intv cc or floating it sets the maximum current sense threshold (for both channels) to one of three different levels (50mv, 100mv, or 75mv, respectively). v fb2 (pin 19): if vprg2 is grounded, this pin receives the remotely sensed feedback voltage for the boost control- ler from an external resistive divider across the output. if vprg 2 is floated or tied to intv cc , this pin receives the remotely sensed output voltage of the boost controller. drvuv (pin 21): determines the higher or lower drv cc uvlo and extv cc switchover thresholds, as listed on the electrical characteristics table. connecting drvuv to gnd chooses the lower thresholds whereas tying drvuv to intv cc chooses the higher thresholds. drvset (pin 22): sets the regulated output voltage of the drv cc ldo regulator. connecting this pin to gnd sets drv cc to 6 v whereas connecting it to intv cc sets drv cc to 10v. voltages between 5v and 10v can be programmed by placing a resistor (50k to 100k) between the drvset pin and gnd. drv cc (pin 24): output of the internal or external low dropout (ldo) regulator. the gate drivers are powered from this voltage source . the drv cc voltage is set by the drvset pin . must be decoupled to ground with a minimum of 4.7 f ceramic or other low esr capacitor . do not use the drv cc pin for any other purpose. extv cc (pin 25): external power input to an internal ldo connected to drv cc . this ldo supplies drv cc power, bypassing the internal ldo powered from v bias whenever extv cc is higher than its switchover threshold (4.7v or 7.7 v depending on the drvset pin). see extv cc connec - tion in the applications information section. do not float or exceed 14 v on this pin. do not connect extv cc to a voltage greater than v bias . connect to gnd if not used. v bias ( pin 26): main supply pin. a bypass capacitor should be tied between this pin and the gnd pin. bg1, bg 2 (pins 31, 27): high current gate drives for bottom n-channel mosfets . voltage swing at these pins is from ground to drv cc . boost1, boost 2 (pins 32, 28): bootstrapped supplies to the topside floating drivers . capacitors are connected between the boost and sw pins. voltage swing at boost 1 is from approximately drv cc to (v in1 + drv cc ). voltage swing at boost2 is from approximately drv cc to (v out2 + drv cc ). ltc 7813 7813f
12 for more information www.linear.com/ltc7813 func t ional diagra m s boost1 drv cc tg1 top bot buck channel 1 s clk pfd sync det vco q r q bot shdn sleep 0.425v top on sw1 bg1 drv cc gnd sense1 + sense1 ? ith1 track/ss1 shdn run1 shdn rst 2(v fb ) foldback 10a v fb1 r a1 r c1 r b1 c c1 0.80v track/ss1 0.88v ov c b1 v in1 v out1 r sense1 l1 switching logic dropout det + ? + ? + ? ? + + i r 3mv i cmp 2.8v 0.65v slope comp + ? + ? c in1 + ? c c1a c ss1 7813 fd01 150na 3.5v 20a freq pllin/mode ilim pgood1 100k ea intv cc ldo drv cc ldo/uvlo control 4.7v/ 7.7v en + ? en 2.00v 1.20v drvset extv cc v in drv cc 20a 4r r + ? + ? drvuv intv cc c out1 + ? + ? 0.88v 0.72v v fb1 ltc 7813 7813f
13 for more information www.linear.com/ltc7813 func t ional diagra m s boost2 drv cc tg2 top bottom clk pllin/mode boost channel 2 s q r q bot shdn sleep 0.425v sw2 bg2 drv cc gnd sense2 ? sense2 + vprg2 ith2 ss2 shdn 10a v fb2 r a2 r c2 r b2 c c2 1.2v ss2 1.32v run2 ov ea c b2 v out2 v in2 v out2 r sense2 l2 switching logic charge pump + ? + ? + ? ? + + i r 3mv i cmp i lim 2.8v 0.7v slope comp + ? + ? c out2 + ? 2v snslo + ? c c2a c ss2 7813 fd02 150na 3.5v snslo c in2 ltc 7813 7813f
14 for more information www.linear.com/ltc7813 o pera t ion main control loop the ltc7813 uses a constant frequency , current mode control architecture . channel 1 is a buck (step-down) controller, and channel 2 is a boost (step-up) controller. during normal operation, the external top mosfet for the buck channel (the external bottom mosfet for the boost controller) is turned on when the clock for that channel sets the rs latch, and is turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp trips and resets the latch is controlled by the voltage on the ith pin, which is the output of the error amplifier, ea. the error amplifier compares the output voltage feedback signal at the v fb pin ( which is generated with an external resistor divider connected across the output voltage, v out , to ground) to the internal 0.800v reference voltage (1.2v reference voltage for the boost). when the load current increases, it causes a slight decrease in v fb relative to the reference , which causes the ea to increase the ith voltage until the average inductor current matches the new load current. after the top mosfet for the buck ( the bottom mosfet for the boost) is turned off each cycle, the bottom mosfet is turned on ( the top mosfet for the boost ) until either the inductor current starts to reverse, as indicated by the cur - rent comparator i r , or the beginning of the next clock cycle. drv cc /extv cc /intv cc power power for the top and bottom mosfet drivers is derived from the drv cc pin. the drv cc supply voltage can be programmed from 5v to 10 v through control of the drvset pin . when the extv cc pin is tied to a voltage below its switchover voltage (4.7v or 7.7v depending on the drvuv voltage ), the v bias ldo (low dropout linear regulator) supplies power from v bias to drv cc . if extv cc is taken above its switchover voltage , the v bias ldo is turned off and an extv cc ldo is turned on. once enabled, the extv cc ldo supplies power from extv cc to drv cc . using the extv cc pin allows the drv cc power to be derived from a high efficiency external source such as the ltc7813 buck regulator output. each top mosfet driver is biased from the floating boot - strap capacitor, c b , which normally recharges during each cycle through an internal switch whenever sw goes low. for buck channel 1, if the input voltage decreases to a voltage close to its output, the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one-twelfth of the clock period every tenth cycle to allow c b to recharge, resulting in about 99% duty cycle. the intv cc supply powers most of the other internal circuits in the ltc7813. the intv cc ldo regulates to a fixed value of 5v and its power is derived from the drv cc supply. shutdown and start-up (run, track/ss pins) the two channels of the ltc7813 can be independently shut down using the run1 and run2 pins. pulling a run pin below 1.22v shuts down the main control loop for that channel. pulling both pins below 0.7v disables both controllers and most internal circuits , including the drv cc and intv cc ldos. in this state, the ltc7813 draws only 3.6a of quiescent current. releasing a run pin allows a small 150na internal current to pull up the pin to enable that controller. each run pin may be externally pulled up or driven directly by logic. each run pin can tolerate up to 65v (absolute maximum), so it can be conveniently tied to v bias in always-on applications where one or both controllers are enabled continuously and never shut down. the start-up of each controllers output voltage v out is controlled by the voltage on the track/ ss pin (track/ss1 for channel 1, ss2 for channel 2). when the voltage on the track / ss pin is less than the 0.8v internal reference for the buck and the 1.2v internal reference for the boost , the ltc7813 regulates the v fb voltage to the track/ss pin voltage instead of the corresponding refer - ence voltage. this allows the track/ ss pin to be used to program a soft-start by connecting an external capacitor from the track / ss pin to gnd. an internal 10 a pull-up current charges this capacitor creating a voltage ramp on the track/ss pin. as the track/ss voltage rises linearly from 0 v to 0.8v/1.2v (and beyond up to about 4v), the output voltage v out rises smoothly from zero (v in for the boost) to its final value. (refer to the functional diagrams) ltc 7813 7813f
15 for more information www.linear.com/ltc7813 o pera t ion alternatively the track/ ss1 pin for the buck channel can be used to cause the start-up of v out1 to track that of another supply. typically , this requires connecting to the track/ ss1 pin an external resistor divider from the other supply to ground ( see the applications information section ). light load current operation (burst mode operation, pulse-skipping or forced continuous mode) (pllin/mode pin) the ltc7813 can be enabled to enter high efficiency burst mode operation, constant frequency pulse-skipping mode, or forced continuous conduction mode at low load currents . to select burst mode operation , tie the pllin/ mode pin to gnd. to select forced continuous operation, tie the pllin/ mode pin to intv cc . to select pulse-skipping mode, tie the pllin/mode pin to a dc voltage greater than 1.1v and less than intv cc C 1.3v. this can be done by connecting a 100k resistor between pllin/mode and intv cc . when a controller is enabled for burst mode operation, the minimum peak current in the inductor is set to ap - proximately 25% of the maximum sense voltage (30% for the boost) even though the voltage on the ith pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier, ea, will decrease the voltage on the ith pin. when the ith volt - age drops below 0.425 v, the internal sleep signal goes high ( enabling sleep mode ) and both external mosfets are turned off. the ith pin is then disconnected from the output of the ea and parked at 0.450v. in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the ltc7813 draws. if one channel is in sleep mode and the other is shut down, the ltc7813 draws only 29a of quiescent current (with drvset = 0v). if both controllers are enabled in sleep mode, the ltc7813 draws only 34a of quiescent cur - rent. in sleep mode, the load current is supplied by the output capacitor . as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the ith pin is reconnected to the output of the ea, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet (the bottom external mosfet for the boost) on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (i r ) turns off the bottom external mosfet ( the top external mosfet for the boost) just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller operates discontinuously. in forced continuous operation , the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the ith pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous operation has the advantage of lower output voltage ripple and less interference to audio circuitry . in forced continuous mode, the output ripple is independent of load current. clocking the ltc7813 from an external source enables forced continuous mode (see the frequency selection and phase-locked loop section). when the pllin/ mode pin is connected for pulse-skipping mode, the ltc7813 operates in pwm pulse-skipping mode at light loads . in this mode, constant frequency operation is maintained down to approximately 1% of designed maximum output current. at very light loads, the current comparator, i cmp , may remain tripped for several cycles and force the external top mosfet (bottom for the boost) to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse ( dis - continuous operation). this mode, like forced continuous operation , exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation . it provides higher low current efficiency than forced continuous mode , but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq and pllin/mode pins) the selection of switching frequency is a trade-off between efficiency and component size . low frequency opera - tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. (refer to the functional diagrams) ltc 7813 7813f
16 for more information www.linear.com/ltc7813 o pera t ion the switching frequency of the ltc7813s controllers can be selected using the freq pin. if the pllin/mode pin is not being driven by an external clock source , the freq pin can be tied to gnd, tied to intv cc or programmed through an external resistor. tying freq to gnd selects 350 khz while tying freq to intv cc selects 535khz. placing a resistor between freq and gnd allows the frequency to be programmed between 50khz and 900khz, as shown in figure 10. a phase-locked loop (pll) is available on the ltc7813 to synchronize the internal oscillator to an external clock source that is connected to the pllin /mode pin. the ltc7813s phase detector adjusts the voltage (through an internal lowpass filter) of the vco input to align the turn-on of tg1 and bg2 to the rising edge of the syn - chronizing signal. the vco input voltage is prebiased to the operating fre - quency set by the freq pin before the external clock is applied . if prebiased near the external clock frequency, the pll loop only needs to make slight changes to the vco input in order to synchronize the rising edge of the external clocks to the rising edge of tg1 and bg2. the ability to prebias the loop filter allows the pll to lock-in rapidly without deviating far from the desired frequency. the typical capture range of the ltc7813s phase-locked loop is from approximately 55khz to 1mhz, with a guaran - tee to be between 75khz and 850khz. in other words, the ltc7813 s pll is guaranteed to lock to an external clock source whose frequency is between 75khz and 850khz. the typical input clock thresholds on the pllin/mode pin are 1.6v (rising) and 1.1v (falling). it is recommended that the external clock source swings from ground (0v) to at least 2.5v. boost controller operation when v in2 > v out2 when the input voltage to the boost channel rises above its regulated v out2 voltage, the controller can behave differently depending on the mode, inductor current and v in2 voltage. in forced continuous mode, the loop works to keep the top mosfet on continuously once v in2 rises above v out2 . an internal charge pump delivers current to the boost capacitor from the boost2 pin to maintain a sufficiently high tg2 voltage. because the ltc7813 uses internal switches and does not require external bootstrap diodes, the charge pump only has to overcome small leakage currents (board leakage, etc.). in pulse-skipping mode, if v in is between 0% and 10% above the regulated v out2 voltage , tg2 turns on if the inductor current rises above approximately 3% of the programmed i lim current. if the part is programmed in burst mode operation under this same v in2 window, then tg2 turns on at the same threshold current as long as the chip is awake (the buck channel is awake and switch - ing). if the buck channel is asleep or shut down in this v in2 window, then tg2 will remain off regardless of the inductor current. if v in rises more than 10% above the regulated v out voltage in any mode, the controller turns on tg2 regard - less of the inductor current. in burst mode operation, however , the internal charge pump turns off if the entire chip is asleep (if the buck channel is also asleep or shut down). with the charge pump off, there would be nothing to prevent the boost capacitor from discharging, result - ing in an insufficient tg2 voltage needed to keep the top mosfet completely on . the charge pump turns back on when the chip wakes up, and it remains on as long as the buck channel is actively switching. boost controller at low sense pin common voltage the current comparator of the boost controller is powered directly from the sense2 + pin and can operate to voltages as low as 2.2v. since this is lower than the v bias uvlo of the chip, v bias can be connected to the output of the boost controller, as illustrated in the typical application circuit in figure?12. this allows the boost controller to handle input voltage transients down to 2.2v while maintaining output voltage regulation. if sense2 + falls below 2.0 v, then switching stops and ss2 is pulled low. if sense2 + rises back above 2.2v, the ss2 pin will be released, initiating a new soft-start sequence. (refer to the functional diagrams) ltc 7813 7813f
17 for more information www.linear.com/ltc7813 o pera t ion buck controller output overvoltage protection the buck channel has an overvoltage comparator that guards against transient overshoots as well as other more serious conditions that may overvoltage the output . when the v fb1 pin rises by more than 10% above its regulation point of 0.800v, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condi - tion is cleared. buck foldback current when the buck output voltage falls to less than 70% of its nominal level, foldback current limiting is activated, progressively lowering the peak current limit in proportion to the severity of the overcurrent or short-circuit condition . foldback current limiting is disabled during the soft-start interval ( as long as the v fb1 voltage is keeping up with the track/ss1 voltage). there is no foldback current limiting for the boost channel. (refer to the functional diagrams) ltc 7813 7813f
18 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion cascaded boost+buck regulator the ltc7813 can be configured to regulate two separate, completely independent outputs, one boost and one buck. or, it can be configured as a cascaded boost+buck single output converter that regulates an output voltage from an input voltage that can be above, below, or equal to the output voltage. when cascaded, the input voltage feeds the boost regulator, which generates an intermediate node supply (v mid ) that then serves as the input to the buck regulator, which then regulates the output voltage. when used as a cascaded boost+buck regulator, the ltc7813 has distinct advantages compared to traditional single inductor buck-boost regulators. even though it requires two inductors, these inductors are individually smaller and provide inherent filtering at the input and output, substantially reducing conducted emi and volt - age ripple, thereby requiring less input and output filter - ing. even though they are cascaded, the boost and buck regulators are independently optimized and compensated . the buck regulator provides a very fast transient response compared to a buck-boost regulator, further reducing the amount of output capacitance that is required. the ltc7813 also features a very low quiescent current burst mode which dramatically reduces power loss and increases efficiency at light loads. thus, for those applications that require low emi , low ripple, fast transient response, low quiescent current , and/ or high light load efficiency, the ltc7813 cascaded boost+buck regulator provides an excellent solution. the typical application on the first page is a basic ltc7813 application circuit . ltc7813 can be configured to use either dcr (inductor resistance) sensing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. dcr sensing has become popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load requirement, and begins with the selection of r sense ( if r sense is used) and inductor value. next, the power mosfets are selected . finally, input and output capacitors are selected. sense + and sense C pins the sense + and sense C pins are the inputs to the cur - rent comparators. buck controller ( sense1 + / sense1 C ): the common mode voltage range on these pins is 0v to 65v (absolute maximum), enabling the ltc7813 to regulate buck output voltages up to a nominal 60 v set point ( allowing margin for tolerances and transients ). the sense 1 + pin is high impedance over the full common mode range, drawing at most 1 a. this high impedance allows the current comparators to be used in inductor dcr sensing . the impedance of the sense1 C pin changes depending on the common mode voltage. when sense1 C is less than intv cc C 0.5 v, a small current of less than 1 a flows out of the pin. when sense1 C is above intv cc + 0.5 v, a higher current (700 a) flows into the pin. between intv cc C 0.5 v and intv cc + 0.5v, the current transitions from the smaller current to the higher current. boost controller ( sense2 + / sense2 C ): the common mode input range for these pins is 2.2v to 60v, allowing the boost converter to operate from inputs over this full range. the sense2 + pin also provides power to the cur - rent comparator and draws about 170a during normal operation ( when not shut down or asleep in burst mode operation). there is a small bias current of less than 1a that flows into the sense2 C pin. this high impedance on the sense2 C pin allows the current comparator to be used in inductor dcr sensing. filter components mutual to the sense lines should be placed close to the ltc7813, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure ?1). sensing cur - rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if dcr sensing is used (figure 2b), r1 should be placed close to the switch - ing node, to prevent noise from coupling into sensitive small-signal nodes . ltc 7813 7813f
19 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion low value resistor current sensing a typical sensing circuit using a discrete resistor is shown in figure 2a. r sense is chosen based on the required output current. the current comparators have a maximum threshold v sense(max) of 50mv, 75mv or 100mv. the current comparator threshold voltage sets the peak of the induc - tor current, yielding a maximum average output current, i max , equal to the peak value less half the peak-to-peak ripple current, ?i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i max + ? i l 2 when using the buck controller in very low dropout condi - tions, the maximum output current level will be reduced due to the internal compensation required to meet stability criteria for buck regulators operating at greater than 50% duty factor . a curve is provided in the typical performance characteristics section to estimate this reduction in peak inductor current depending upon the operating duty factor. inductor dcr sensing for applications requiring the highest possible efficiency at high load currents, the ltc7813 is capable of sensing the voltage drop across the inductor dcr, as shown in figure?2 b. the dcr of the inductor represents the small amount of dc winding resistance of the copper , which can be less than 1m for todays low value, high current inductors. in a high current application requiring such an inductor, power loss through a sense resistor would cost several points of efficiency compared to inductor dcr sensing. 7813 f01 to sense filter next to the controller inductor or r sense current flow figure 1. sense lines placement with inductor or sense resistor figure 2. current sensing methods 7813 f02a ltc7813 boost tg sw bg sense1 + (sense2 ? ) sense1 ? (sense2 + ) gnd v in1 (v out2 ) v out1 (v in2 ) r sense cap placed near sense pins 7813 f02b ltc7813 boost tg sw bg sense1 + (sense2 ? ) sense1 ? (sense2 + ) gnd v in1 (v out2 ) v out1 (v in2 ) c1* r2 *place c1 near sense pins r sense(eq) = dcr(r2/(r1+r2)) l dcr inductor r1 (r1||r2) ? c1 = l/dcr (2a) using a resistor to sense current (2b) using the inductor dcr to sense current if the external (r1||r2) t c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/( r1 + r 2). r 2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external filter components , the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers data sheets for detailed information. ltc 7813 7813f
20 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion using the inductor ripple current value from the inductor value calculation section , the target sense resistor value is: r sense(equiv) = v sense(max) i max + ? i l 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for v sense(max) in the electrical charac - teristics table. next , determine the dcr of the inductor. when provided, use the manufacturer s maximum value, usually given at 20c. increase this value to account for the temperature coefficient of copper resistance, which is approximately 0.4%/c. a conservative value for t l(max) is 100c. to scale the maximum inductor dcr to the desired sense resistor value (r d ), use the divider ratio: r d = r sense(equiv) dcr max at t l(max) c1 is usually selected to be in the range of 0.1f to 0.47f. this forces r 1|| r2 to around 2k, reducing error that might have been caused by the sense 1 + /sense2 C pin s 1a current. the equivalent resistance r1||r2 is scaled to the tempera - ture inductance and maximum dcr: ? r1 ? r2 = l (dcr at 20 c) ? c1 the sense resistor values are: ? r1 = r1 ? r2 r d ; r2 = r1 ? r d 1 ? r d the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p loss r1 = v in(max) ? v out ( ) ? v out r1 for the boost controller, the maximum power loss in r1 will occur in continuous mode at v in = 1/2 ? v out : p loss r1 = v out(max) ? v in ( ) ? v in r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads , consider this power loss when deciding whether to use dcr sensing or sense resistors . light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. inductor value calculation the operating frequency and inductor selection are inter - related in that higher operating frequencies allow the use of smaller inductor and capacitor values . so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet switching and gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current, ?i l , decreases with higher inductance or higher frequency. for the buck controllers, ?i l increases with higher v in : ? i l = 1 f ( ) l ( ) v out 1 ? v out v in ? ? ? ? ? ? for the boost controller, ?i l increases with higher v out : ? i l = 1 f ( ) l ( ) v in 1 ? v in v out ? ? ? ? ? ? accepting larger values of ?i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses . a reasonable starting point for setting ripple current is ?i l = 0.3(i max ). the maximum ?i l occurs at the maximum input voltage for the bucks and v in = 1/2 ? v out for the boost. ltc 7813 7813f
21 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion the inductor value also has secondary effects . the tran - sition to burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit (30% for the boost) determined by r sense . lower inductor values (higher ?i l ) will cause this to occur at lower load currents , which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance value selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred for high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. ferrite core material saturates hard , which means that induc - tance collapses abruptly when the peak design current is exceeded . this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet selection two external power mosfets must be selected for each controller in the ltc7813: one n-channel mosfet for the top switch (main switch for the buck, synchronous for the boost), and one n-channel mosfet for the bottom switch (main switch for the boost, synchronous for the buck). the peak-to-peak drive levels are set by the drv cc volt- age. this voltage can range from 5v to 10v depending on c o nfiguration of the drvset pin . therefore , both logic-level and standard-level threshold mosfets can be used in most applications depending on the programmed drv cc voltage. pay close attention to the bv dss specification for the mosfets as well. the ltc7813 s unique ability to adjust the gate drive level between 5 v to 10v (opti-drive) allows an application circuit to be precisely optimized for efficiency . when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if a change is made and the input current decreases , then the efficiency has im - proved. if there is no change in input current, then there is no change in efficiency . selection criteria for the power mosfet s include the on-resistance r ds(on) , miller capacitance c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: buck main switch duty cycle = v out v in buck sync switch duty cycle = v in ? v out v in boost main switch duty cycle = v out ? v in v out boost sync switch duty cycle = v in v out ltc 7813 7813f
22 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion the mosfet power dissipations at maximum output current are given by: p main _ buck = v out v in i out(max) ( ) 2 1 + ( ) r ds(on) + (v in ) 2 i out(max) 2 ? ? ? ? ? ? (r dr )(c miller ) ? 1 v drvcc ? v thmin + 1 v thmin ? ? ? ? ? ? (f) p sync _ buck = v in ? v out v in i out(max) ( ) 2 1 + ( ) r ds(on) p main _ boost = v out ? v in ( ) v out v in 2 i out(max) ( ) 2 ? 1 + ( ) r ds(on) + v out 3 v in ? ? ? ? ? ? i out(max) 2 ? ? ? ? ? ? ? r dr ( ) c miller ( ) ? 1 v drvcc ? v thmin + 1 v thmin ? ? ? ? ? ? (f) p sync _ boost = v in v out i out(max) ( ) 2 1 + ( ) r ds(on) where is the temperature dependency of r ds(on) and r dr (approximately 2) is the effective driver resistance at the mosfets miller threshold voltage. v thmin is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the main n-channel equations for the buck and boost controllers include an additional term for transition losses, which are highest at high input voltages for the buck and low input voltages for the boost . for v in < 20v ( higher v in for the boost ) the high current efficiency generally improves with larger mosfets, while for v in > 20v ( lower v in for the boost) the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actu- ally provides higher efficiency. the synchronous mosfet losses for the buck controller are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve , but = 0.005/c can be used as an approximation for low voltage mosfets. boost c in , c out selection the input ripple current in a boost converter is relatively low ( compared with the output ripple current), because this current is continuous. the boost input capacitor c in voltage rating should comfortably exceed the maximum input voltage. although ceramic capacitors can be relatively tolerant of overvoltage conditions , aluminum electrolytic capacitors are not. be sure to characterize the input voltage for any possible overvoltage transients that could apply excess stress to the input capacitors. the value of c in is a function of the source impedance , and in general, the higher the source impedance, the higher the required input capacitance . the required amount of input capacitance is also greatly affected by the duty cycle. high output current applications that also experience high duty cycles can place great demands on the input supply, both in terms of dc current and ripple current. in a boost converter, the output has a discontinuous current, so c out must be capable of reducing the output voltage ripple. the effects of esr (equivalent series resistance) and the bulk capacitance must be considered when choos - ing the right capacitor for a given output ripple voltage . the steady ripple due to charging and discharging the bulk capacitance is given by : ripple = i out(max) ? v out ? v in(min) ( ) c out ? v out ? f v where c out is the output filter capacitor. the steady ripple due to the voltage drop across the esr is given by: ?v esr = i l(max) ? esr multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum , special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount ltc 7813 7813f
23 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion packages. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient. capacitors are now available with low esr and high ripple current ratings such as os-con and poscap. buck c in , c out selection the selection of c in is usually based off the worst-case rms input current. the highest (v out )(i out ) product needs to be used in the formula shown in equation 1 to determine the maximum rms capacitor current requirement. in continuous mode , the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in C v out ( ) ? ? ? ? 1/ 2 (1) this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc7813, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. a small (0.1f to 1f) bypass capacitor between the chip v in pin and ground, placed close to the ltc7813, is also suggested. a small (10) resistor placed between c in (c1) and the v in pin provides further isolation. the selection of c out is driven by the effective series resistance (esr). typically , once the esr requirement is satisfied , the capacitance is adequate for filtering. the output ripple (v out ) is approximated by: ? v out ? i l esr + 1 8 ? f ? c out ? ? ? ? ? ? where f is the operating frequency, c out is the output capacitance and i l is the ripple current in the inductor. the output ripple is highest at maximum input voltage since i l increases with input voltage. setting buck output voltage the ltc7813 output voltage for the buck controller is set by an external feedback resistor divider carefully placed across the output, as shown in figure ?3. the regulated output voltage is determined by: v out(buck) = 0.8v 1 + r b r a ? ? ? ? ? ? to improve the frequency response , a feedforward ca - pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources , such as the inductor or the sw line. 7813 f03 ltc7813 v fb1 r b c ff r a v out1 figure 3. setting buck output voltage setting boost output voltage (vprg2 pin) through control of the vprg2 pin, the boost controller output voltage can be set by an external feedback resis - tor divider or programmed to a fixed 10v or 12v output. grounding vprg 2 allows the boost output voltage to be set by an external feedback resistor divider placed across the output, as shown in figure 4a. the regulated output voltage is determined by: v out(boost) = 1.2v 1 + r b r a ? ? ? ? ? ? tying the vprg 2 to intv cc or floating it configures the boost controller in fixed output voltage mode. figure 4b shows how the v fb2 pin is used to sense the output ltc 7813 7813f
24 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion voltage in this mode. tying vprg 2 to intv cc programs the boost output to 12v, whereas floating vprg2 programs the output to 10v. 7813 f04a ltc7813 v fb2 vprg2 gnd r b c ff r a v out2 (4a) setting boost output using external resistors 7813 f04b ltc7813 (4b) setting boost to fixed 12v/10v output v fb2 vprg2 intv cc /float c out v out2 12v/10v figure 4. setting boost output voltage run pins the ltc7813 is enabled using the run1 and run2 pins. the run pins have a rising threshold of 1.275v with 75mv of hysteresis. pulling a run pin below 1.2v shuts down the main control loop for that channel. pulling all three run pins below 0.7v disables the controllers and most internal circuits , including the drv cc and intv cc ldos. in this state, the ltc7813 draws only 3.6a of quiescent current. releasing a run pin allows a small 150na internal current to pull up the pin to enable that controller. because of condensation or other small board leakage pulling the pin down, it is recommended the run pins be externally pulled up or driven directly by logic. each run pin can tolerate up to 65v (absolute maximum), so it can be conveniently tied to v bias in always-on applications where one or more controllers are enabled continuously and never shut down. the run pins can be implemented as a uvlo by con - necting them to the output of an external resistor divider network off v bias , as shown in figure?5. the rising and falling uvlo thresholds are calculated using the run pin thresholds and pull-up current: v uvlo(rising) = 1.275v 1 + r b r a ? ? ? ? ? ? C 150na ? r b v uvlo(falling) = 1.20v 1 + r b r a ? ? ? ? ? ? C 150na ? r b tracking and soft-start (track/ss1 and ss2 pins) the start-up of each v out is controlled by the voltage on the track/ ss pin (track/ss1 for channel 1, ss2 for channel 2). when the voltage on the track /ss pin is less than the internal 0.8v reference (1.2v reference for the boost channel), the ltc7813 regulates the v fb pin voltage to the voltage on the track/ss pin instead of the internal reference. the track/ss pin can be used to program an external soft-start function or to allow v out to track another supply during start-up. soft-start is enabled by simply connecting a capacitor from the track/ss pin to ground, as shown in figure ?6. an internal 10 a current source charges the capacitor, providing a linear ramping voltage at the track/ss pin. the ltc7813 will regulate its feedback voltage (and hence v out ) according to the voltage on the track/ss pin, al - lowing v out to rise smoothly from 0v (v in for the boost) 7813 f05 ltc7813 run r b r a v bias figure 5. using the run pins as a uvlo 7813 f06 ltc7813 track/ss gnd c ss figure 6. using the track/ss pin to program soft-start ltc 7813 7813f
25 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion to its final regulated value. the total soft-start time will be approximately: t ss _ buck = c ss ? 0.8v 10a t ss _ boost = c ss ? 1.2v 10a alternatively, the track/ ss1 pin for the buck controller can be used to track another supply during start-up, as shown qualitatively in figures?7 a and 7b. to do this , a resistor divid - er should be connected from the master supply (v x ) to the track/ss pin of the slave supply (v out ), as shown in figure?8. during start-up v out will track v x according to the ratio set by the resistor divider: v x v out = r a r tracka ? r tracka + r trackb r a + r b for coincident tracking (v out = v x during start-up), r a = r tracka r b = r trackb drv cc and intv cc regulators (opti-drive) the ltc7813 features two separate internal p-channel low dropout linear regulators (ldo) that supply power at the drv cc pin from either the v bias supply pin or the extv cc pin depending on the connections of the extv cc and drvset pins . a third p-channel ldo supplies power at the intv cc pin from the drv cc pin. drv cc powers the gate drivers whereas intv cc powers much of the ltc7813 s internal circuitry . the v bias ldo and the extv cc ldo regulate drv cc between 5v to 10v, depending on how the drvset pin is set . each of these ldos can supply a peak current of at least 50ma and must be bypassed to ground with a minimum of 4.7 f ceramic capacitor. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent in - teraction between the channels. the intv cc supply must be bypassed with a 0.1f ceramic capacitor. 7813 f07a v x(master) v out(slave) output (v out ) time (7a) coincident tracking 7813 f07b v x(master) v out(slave) output (v out ) time (7b) ratiometric tracking 3899 f09 ltc7813 v fb1 track/ss1 r b r a v out r trackb r tracka v x figure 7. tw o different modes of output voltage tracking figure 8. using the track/ss1 pin for tracking ltc 7813 7813f
26 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion the drvset pin programs the drv cc supply voltage and the drvuv pin selects different drv cc uvlo and extv cc switchover threshold voltages . table 1 a summarizes the different drvset pin configurations along with the volt - age settings that go with each configuration. table 1b summarizes the different drvuv pin settings . tying the drvset pin to intv cc programs drv cc to 10v. tying the drvset pin to gnd programs drv cc to 6v. by placing a 50 k to 100 k resistor between drvset and gnd the drv cc voltage can be programmed between 5 v to 10v, as shown in figure 8. table 1a drvset pin drv cc voltage gnd 6v intv cc 10v resistor to gnd 50k to 100k 5v to 10v table 1b drvuv pin drv cc uvlo rising / falling thresholds ext v cc switchover rising/falling threshold 0v 4.0v / 3.8v 4.7v / 4.45v intv cc 7.5v / 6.7v 7.7v / 7.45v ldo or the extv cc ldo. when the voltage on the extv cc pin is less than its switchover threshold (4.7 v or 7.7 v as determined by the drvset pin described above ), the v bias ldo is enabled. power dissipation for the ic in this case is highest and is equal to v bias ? i drvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section. the junction tem - perature can be estimated by using the equations given in note 2 of the electrical characteristics. for example, using the ltc7813 in the qfn package, the drv cc current is limited to less than 21ma from a 60v supply when not using the extv cc supply at a 70c ambient temperature: t j = 70c + (21ma)(60v)(44c/w) = 125c to prevent the maximum junction temperature from be - ing exceeded, the v bias supply current must be checked while operating in forced continuous mode (pllin/mode = intv cc ) at maximum v bias . when the voltage applied to extv cc rises above its switch over threshold, the v bias ldo is turned off and the extv cc ldo is enabled. the extv cc ldo remains on as long as the voltage applied to extv cc remains above the switchover threshold minus the comparator hysteresis. the extv cc ldo attempts to regulate the drv cc voltage to the voltage as programmed by the drvset pin , so while extv cc is less than this voltage, the ldo is in dropout and the drv cc voltage is approximately equal to extv cc . when extv cc is greater than the programmed voltage , up to an absolute maximum of 14v, drv cc is regulated to the programmed voltage. using the extv cc ldo allows the mosfet driver and control power to be derived from the ltc7813s buck output (4.7v/7.7v v out 14v) during normal opera - tion and from the v bias ldo when the output is out of regulation (e.g., start-up , short circuit). if more current is required through the extv cc ldo than is specified, an external schottky diode can be added between the extv cc and drv cc pins. in this case, do not apply more than 10v to the extv cc pin and make sure that extv cc v bias . significant efficiency and thermal gains can be realized by powering drv cc from the output, since the v in cur - rent resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). drvset pin resistor (k) 50 4 drv cc voltage (v) 5 7 8 9 11 55 75 85 7813 f09 6 10 70 95 100 60 65 80 90 figure 9. relationship between drv cc voltage and resistor value at drvset pin high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi - mum junction temperature rating for the ltc7813 to be exceeded . the drv cc current, which is dominated by the gate charge current, may be supplied by either the v bias ltc 7813 7813f
27 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion for 5 v to 14v regulator outputs, this means connecting the extv cc pin directly to v out . tying the extv cc pin to an 8.5 v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (21ma)(8.5v)(44c/w) = 78c however, for 3.3v and other low voltage outputs, additional circuitry is required to derive drv cc power from the output. the following list summarizes the four possible connec- tions for extv cc : 1. extv cc grounded. this will cause drv cc to be powered from the internal v bias regulator resulting in increased power dissipation in the ltc7813 at high input voltages . 2. extv cc connected directly to the output of the buck regulator. this is the normal connection for a 5v to 14v regulator and provides the highest efficiency. 3. extv cc connected to an external supply. if an external supply is available in the 5v to 14v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. ensure that extv cc v bias . 4. extv cc connected to an output-derived boost network off of the buck regulator. for 3.3v and other low volt - age regulators, efficiency gains can still be realized by connecting ext v cc to an output-derived voltage that has been boosted to greater than 4.7v/7.7v. ensure that extv cc v bias . topside mosfet driver supply (c b ) external bootstrap capacitors, c b , connected to the boost pins supply the gate drive voltage for the topside mosfet. the ltc7813 features an internal switch between drv cc and the boost pin for each controller . these internal switches eliminate the need for external bootstrap diodes between drv cc and boost. capacitor c b in the functional diagram is charged through this internal switch from drv cc when the sw pin is low. when the topside mosfet is to be turned on , the driver places the c b voltage across the gate-source of the mosfet . this enhances the top mos - fet switch and turns it on. the switch node voltage, sw, rises to v in and the boost pin follows . with the topside mosfet on , the boost voltage is above the input supply: v boost = v in + v drvcc (v boost = v out + v drvcc for the boost controller). the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet(s). fault conditions: buck current limit and current foldback the ltc 7813 includes current foldback for the buck chan - nel to help limit load current when the output is shorted to ground . if the buck output voltage falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 100% to 40% of its maximum selected value . under short-circuit conditions with very low duty cycles , the buck channel will begin cycle skipping in order to limit the short-circuit current . in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short-circuit ripple current is determined by the minimum on-time, t on( min) , of the ltc7813 (80ns), the input voltage and inductor value: ? i l(sc) = t on(min) v in l ? ? ? ? ? ? the resulting average short-circuit current is: i sc = 40% ? i lim(max) ? 1 2 ? i l(sc) fault conditions: buck overvoltage protection (crowbar) the overvoltage crowbar is designed to blow a system input fuse when the output voltage of the buck regula - tor rises much higher than nominal levels . the crowbar causes huge currents to flow , that blow the fuse to protect against a shorted top mosfet if the short occurs while the controller is operating. a comparator monitors the buck output for overvoltage conditions. the comparator detects faults greater than 10% above the nominal output voltage. when this condition is sensed, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. the bottom mosfet remains on continuously for as long as the overvoltage condition persists ; if v out returns to a safe level, normal operation automatically resumes. ltc 7813 7813f
28 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion a shorted top mosfet will result in a high current condition which will open the system fuse. the switching regulator will regulate properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage. fault conditions: overtemperature protection at higher temperatures, or in cases where the internal power dissipation causes excessive self heating on chip ( such as drv cc short to ground), the overtemperature shutdown circuitry will shut down the ltc7813. when the junction temperature exceeds approximately 175c, the overtemperature circuitry disables the drv cc ldo, causing the drv cc supply to collapse and effectively shutting down the entire ltc7813 chip. once the junction temperature drops back to the approximately 155c, the drv cc ldo turns back on. long-term overstress (t j > 125c) should be avoided as it can degrade the performance or shorten the life of the part. phase-locked loop and frequency synchronization the ltc7813 has an internal phase-locked loop (pll) comprised of a phase frequency detector, a lowpass filter, and a voltage-controlled oscillator (vco). this allows the turn-on of tg1 and bg2 to be locked to the rising edge of an external clock signal applied to the pllin / mode pin. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. if the external clock frequency is greater than the inter - nal oscillators frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the vco input. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the vco input. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage at the vco input is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the internal filter capacitor, holds the voltage at the vco input. note that the ltc7813 can only be synchronized to an external clock whose frequency is within range of the ltc7813s internal vco, which is nominally 55khz to 1 mhz. this is guaranteed to be between 75khz and 850khz. typically, the external clock (on the pllin/mode pin) input high threshold is 1.6v, while the input low threshold is 1.1v. the ltc7813 is guaranteed to synchronize to an external clock that swings up to at least 2.5v and down to 0.5v or less. rapid phase locking can be achieved by using the freq pin to set a free-running frequency near the desired synchronization frequency. the vcos input voltage is prebiased at a frequency corresponding to the frequency set by the freq pin. once prebiased, the pll only needs to adjust the frequency slightly to achieve phase lock and synchronization. although it is not required that the free- running frequency be near the external clock frequency, doing so will prevent the operating frequency from passing through a large range of frequencies as the pll locks. freq pin resistor (k) 15 frequency (khz) 600 800 1000 35 45 55 25 7813 f10 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125 figure 10. relationship between oscillator frequency and resistor value at the freq pin ltc 7813 7813f
29 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion table 2 summarizes the different states in which the freq pin can be used. table 2 freq pin pllin/mode pin frequency 0v dc voltage 350khz intv cc dc voltage 535khz resistor to gnd dc voltage 50khz to 900khz any of the above external clock 75khz to 850khz phase locked to external clock minimum on-time considerations minimum on-time , t on(min) , is the smallest time duration that the ltc7813 is capable of turning on the top mosfet ( bottom mosfet for the boost controller ). it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min)_ buck < v out v in (f) t on(min)_ boost < v out ? v in v out (f) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc7813 is approximately 80ns for the buck and 120ns for the boost. however, for the buck channels as the peak sense voltage decreases the minimum on-time gradually increases up to about 130ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc7813 circuits : 1) ic v bias current , 2) drv cc regulator current , 3) i 2 r losses , 4) topside mosfet transition losses. 1. the v bias current is the dc supply current given in the electrical characteristics table, which excludes mos - fet driver and control currents. v bias current typically results in a small (<0.1%) loss. 2. drv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again , a packet of charge, dq, moves from drv cc to ground. the resulting dq/dt is a cur - rent out of drv cc that is typically much larger than the control circuit current . in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying drv cc from an output-derived source power through extv cc will scale the v in current required for the driver and control circuits by a factor of ( duty cycle)/ (efficiency). for example, in a 20 v to 5 v application, 10 ma of drv cc current results in approximately 2.5ma of v in current. this reduces the midcurrent loss from 10% or more ( if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse ( if used), mosfet, inductor, current sense resis- tor and input and output capacitor esr. in continuous mode the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet . if the two mosfets have approximately the same r ds(on) , then the resis - tance of one mosfet can simply be summed with the resistances of l , r sense and esr to obtain i 2 r losses. ltc 7813 7813f
30 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion for example, if each r ds(on) = 30m, r l = 50m, r sense = 10m and r esr = 40m ( sum of both input and output capacitance losses), then the total resistance is 130m. this results in losses ranging from 3% to 13% as the output current increases from 1a to 5a for a 5 v output, or a 4% to 20% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the top mosfet (s) (bot - tom mosfet for the boost), and become significant only when operating at high input ( output for the boost) voltages ( typically 20 v or greater). transition losses can be estimated from: t ransition loss = (1.7) ? v in 2 ? i o(max) ? c rss ? f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. other losses including schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load(esr) , where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recov - ery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem . opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values . the availability of the ith pin not only allows optimization of control loop behavior, but it also provides a dc-coupled and ac-filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/ or damping factor can be estimated using the percentage of overshoot seen at this pin . the bandwidth can also be estimated by examining the rise time at the pin . the ith external components shown in figure ?12 circuit will provide an adequate starting point for most applications. the ith series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase . an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output ca - pacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response . the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by de - creasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. ltc 7813 7813f
31 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise-time should be controlled so that the load rise-time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. buck design example as a design example for the buck channel, assume v in = 12v (nominal), v in = 22v (maximum), v out = 3.3v, i max = 5a, v sense(max) = 75 mv and f = 350khz. the induc - tance value is chosen first based on a 30% ripple current assumption . the highest value of ripple current occurs at the maximum input voltage. tie the freq pin to gnd, generating 350 khz operation . the minimum inductance for 30% ripple current is: ? i l = v out f ( ) l ( ) 1 ? v out v in(nom) ? ? ? ? ? ? ? ? a 4.7 h inductor will produce 29% ripple current. the peak inductor current will be the maximum dc value plus one half the ripple current, or 5.73a. increasing the ripple current will also help ensure that the minimum on-time of 80 ns is not violated. the minimum on-time occurs at maximum v in : t on(min) = v out v in(max) f ( ) = 3.3v 22v 350khz ( ) = 429ns the equivalent r sense resistor value can be calculated by using the minimum value for the maximum current sense threshold (65mv): r sense 65mv 5.73a 0.01 choosing 1% resistors: r a = 25 k and r b = 78.7 k yields an output voltage of 3.32v. the power dissipation on the topside mosfet can be easily estimated. choosing a fairchild fds6982s dual mosfet results in: r ds(on) = 0.035/0.022, c miller = 215pf. at maximum input voltage with t(estimated) = 50c: p main = 3.3v 22v 5a ( ) 2 1 + 0.005 ( ) 50 c ? 25 c ( ) ? ? ? ? 0.035 ( ) + 22v ( ) 2 5a 2 2.5 ( ) 215pf ( ) ? 1 6v ? 2.3v + 1 2.3v ? ? ? ? ? ? 350khz ( ) = 308mw a short-circuit to ground will result in a folded back cur - rent of: i sc = 34mv 0.01 ? 1 2 80ns 22v ( ) 4.7h ? ? ? ? ? ? = 3.21a with a typical value of r ds(on) and = (0.005/c)(25c) = 0.125. the resulting power dissipated in the bottom mosfet is: p sync = (3.21a) 2 (1.125) (0.022) = 255mw which is less than under full-load conditions. c in is chosen for an rms current rating of at least 3a at temperature assuming only this channel is on. c out is chosen with an esr of 0.02 for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage . the output voltage ripple due to esr is approximately: v o(ripple) = r esr (?i l ) = 0.02 (1.45a) = 29mv p-p pc board layout checklist when laying out the printed circuit board , the following checklist should be used to ensure proper operation of the ic. figure ?11 illustrates the current waveforms present in the various branches of the synchronous boost and buck regulators operating in the continuous mode. check the following in your layout: 1. are the signal and power grounds kept separate ? the combined ic signal ground pin and the ground return of c drvcc must return to the combined c out (C) terminals . the path formed by the top n-channel mosfet, bottom n-channel mosfet , and the c in capacitor should have ltc 7813 7813f
32 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the mosfet loop described above. 2. does the ltc7813 v fb pins resistive divider connect to the (+) terminal of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground. the feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 3. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. 4. is the drv cc and decoupling capacitor connected close to the ic, between the drv cc and the ground pin? this capacitor carries the mosfet drivers current peaks. 5. keep the switching nodes (sw1, sw2), top gate (tg1, tg2), and boost nodes (boost1, boost2) away from sensitive small-signal nodes, especially from the other channel s voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc7813 and occupy minimum pc trace area. 6. use a modified star ground technique: a low impedance , large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the drv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the gnd pin of the ic. pc board layout debugging start with one controller at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit . monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application . the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold typi- cally 25% of the maximum designed current level in burst mode operation. t he duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug - gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensation of the loop can be used to tame a poor pc layout if regula - tor bandwidth optimization is not required. only after each controller is checked for its individual performance should both should multiple controllers be turned on at the same time. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un- dervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out - put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents , look for capacitive coupling between the boost , sw, tg, and possibly bg connections and the sensitive voltage and current pins . the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages , look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the gnd pin of the ic. an embarrassing problem, which can be missed in an otherwise properly working switching regulator , results when the current sensing leads are hooked up backwards. the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordon t worry, the regulator will still maintain control of the output voltage. ltc 7813 7813f
33 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion figure 11. branch current waveforms r l2 l2 sw2 r sense2 r in v in v out2 c out2 7813 f11a bold lines indicate high switching current. keep lines to a minimum length. v r l1 l1 sw1 r sense1 v out1 c out1 v in c in r in bold lines indicate high switching current. keep lines to a minimum length. 7813 f11b (a) boost regulator (b) buck regulator ltc 7813 7813f
34 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion compensation and v mid capacitance in a cascaded boost+buck regulator when using the ltc7813 as a cascaded boost+buck regulator, the boost and buck regulator control loops are compensated individually. while this may seem more complicated, this is actually advantageous, as the inher - ently fast buck loop can be designed to handle the output load transient , while the boost loop is less important and can be slower. the amount of capacitance needed on the intermediate v mid node ( boost output ) and the buck output v out depends on a number of factors, including the input voltage, output voltage, load current and the nature of any transients, and the mode of operation (burst mode operation, forced continuous mode, or pulse-skipping mode). in general, the buck regulator should be designed to handle any output load transients and provide sufficiently low output ripple. the boost regulator does not need to respond as fast, as the v mid node can tolerate relatively high ripple and /or transient dips and therefore does not necessarily need a lot of capacitance. the v mid node capacitance needs to be able to handle the input ripple current from the buck regulator. it also needs to be large enough that the boost regulators voltage ripple and/or transient dips do not ap - pear as significant input line steps to the buck regulator and feed through to the buck regulator s output. the ripple on the v mid node is higher in burst mode opera - tion and pulse-skipping mode than in forced continuous mode , especially at light loads and/or if the input voltage is slightly below the regulated boost output (v mid ) voltage . thus, burst mode operation and pulse-skipping mode generally require more v mid capacitance than in forced continuous mode to maintain a similar amount of ripple . the capacitance on the v mid node can be all ceramic, or some combination of ceramic and polarized (tantalum, electrolytic, etc.) capacitors. choosing the v mid voltage in cascaded boost+buck regulator there are many performance trade-offs when considering where to set the v mid ( boost output) regulation voltage (v mid_reg ) relative to the input voltage (v in ) range and output (buck) regulation voltage (v out_reg ). these trade- offs include efficiency, quiescent current, switching noise/ emi, and voltage ripple. remember that v mid will follow v in if v in > v mid_reg (see the boost controller operation when v in > v out section in the operation section). if v in < v mid_reg , v mid is regulated to v mid_reg . consider as an example an automotive application that requires a regulated 12 v output voltage generated from a vehicle battery . the battery spends most of its operating lifetime in a normal range of 10v to 16v, but may dip to as low as 2.5v during engine start and rise as high as 38v during high voltage transients. we can designate the minimum normal operating voltage as v in_min_op = 10v, and the maximum normal operating voltage as v in_max_op = 16v. so what voltage should we choose for v mid_reg ? regulated output voltage in this example, note that we want a tightly regulated output (v out_reg =12v), which is within our normal operating range (v in_min_op < v out_reg < v in_max_op ). we want v mid_reg > v out_reg to provide headroom for the buck regulator, but we have a choice of whether to set v mid_reg above or below v in_max_op . option a : v mid _ reg > v out _ reg and v mid _ reg > v in_max_op in this option, we set v mid_ reg > v in_ max_ op (e.g ., v mid_reg =18v). both the boost regulator and the buck regulator are switching (at full, constant frequency if in forced continuous mode ) over the full 10v to 16v nor - mal operating range. since the boost regulator is always switching, the efficiency is lower and the input ripple and emi, while predictable and still low, are higher than other potential options. ltc 7813 7813f
35 for more information www.linear.com/ltc7813 a pplica t ions i n f or m a t ion option b : v in_ min _ op < v out _ reg < v mid _ reg < v in_ max _ op this is similar to option a, but v mid_reg is set within the normal operating input voltage range (e.g., v mid_reg =14v). when v in is well below v mid_reg , this option is like option a. but as v in approaches v mid_reg , the boost controller will gradually begin skipping cycles (even in forced continuous mode ) once it reaches minimum-on- time. if v in > v mid_reg , then v mid follows v in . in this region, option b is more efficient than option a since the boost is not switching. but this is at the expense of the cycle-skipping (non-constant frequency ripple) when v in is slightly below v mid_reg . loosely regulated output ( pass-through regulator) in some applications, it is not critical that v out be tightly regulated, but rather that it remains within a certain voltage range. suppose, in our example, that it is only important that v out be maintained within the normal battery operating voltage range of 10v to 16 v. we can consider a third option : option c : v mid_ reg = v in_ min_ op and v out_ reg = v in_max_op here we set v mid_reg = v in_min_op =10 v and v out_reg = v in_max_op =16v. so the boost regulator only boosts when v in < 10 v and the buck regulator only bucks when v in >16v. when v in is between 10v to 16v, the circuit is in a pass-through or wire mode where there is very little switching. the boost regulator is not boosting (tg2 is on 100% in forced continuous mode) and the buck regulator is operating in dropout (with tg1 on at an effec - tive 99% duty cycle ). this makes the circuit very efficient, especially at heavy loads, with extremely low input and output ripple and emi. note that in this pass-through mode, the circuit does not benefit from the ltc7813s ultralow quiescent current of 33a in burst mode operation since the buck regulator does not go to sleep because v out < v out_reg =16v. regulated output voltage below normal input voltage operating range in some applications, the desired output voltage might be less than the minimum normal operating voltage , but still higher than the worst case minimum input voltage. consider our previous example, but instead suppose we want v out = 5v. in this case, we can set our v mid_reg such that: option d: v in_min_op > v mid_reg > v out_reg so we might set v mid_reg just below 10v, so that the boost regulator never switches within the normal operating range and only needs to boost during the input voltage dips below 10v. the buck controller always regulates the v out to 5v, and the boost regulators inductor and v mid capacitance cre - ate a filter that substantially reduces any input ripple and results in ver y little conducted emi on the input. t able 3 summarizes some of the performance trade-offs of these four potential ways to set the v mid regulation voltage in an ltc7813 cascaded boost+buck regulator. ltc 7813 7813f
36 for more information www.linear.com/ltc7813 table 3. summary of trade-offs in choosing the v mid regulation voltage in a cascaded boost+buck regulator a b c d option v mid_reg > v out_reg and v mid_reg > v in_max_op v in_min_op < v out_reg < v mid_reg < v in_max_op v mid_reg = v in_min_op and v out_reg = v in_max_op (pass-through/wire mode) v in_min_op > v mid_reg > v out_reg example for normal input operating range of 10v to 16v (v in_min_op = 10v, v in_max_op = 16v) with a full range of 2.5v to 38v v mid_reg =18v v out = v out_reg = 12v v mid_reg = 14v v out = v out_reg = 12v v mid_reg =10v v out_reg = 16v v out = 10v to 16v v mid_reg =10v v out = v out_reg = 5v boost boosting in normal operating range? yes , over full range yes , when v in < v mid_reg no no buck bucking in normal operating range? yes , over full range yes , over full range no, in dropout yes , over full range ltc7813 no load quiescent current in burst mode 34a 34a ~3ma 34a heavy load efficiency slightly lower high when not boosting; slightly lower when boosting highest high input ripple low low when boosting; very low when not boosting; some cycle-skipping during transition extremely low very low output ripple low low extremely low low emi in normal operating range low very low when not boosting; low when boosting extremely low very low example for normal operating range: v in_min_op = 10v C v in_max_op = 16v v mid_reg =18v v out = v out_reg = 12v v mid_reg =14v v out = v out_reg = 12v v mid_reg =10v v out_reg = 16v v out = 10v to 16v v mid_reg =10v v out = v out_reg = 5v a pplica t ions i n f or m a t ion ltc 7813 7813f
37 for more information www.linear.com/ltc7813 typical a pplica t ions figure 12. wide input range to 12v/8a low i q cascaded boost+buck regulator (v mid = 14v) ltc 7813 7813f c in1 33f c in2,3,4 6.8f 2m r sense2 1000pf l2 11h l1 4.7h m bot2 0.1f m top2 c b2 0.1f c mid1,2,3 6.8f c mid4 33f m top1 m bot1 c b1 100pf 0.1f 3m r sense1 r b2 499k r a2 46.4k c out1 22f c out2,3 4.7nf 47f c ss1 0.1f c ss2 0.1f sense2 + sense2 ? bg2 sw2 boost2 15k tg2 intv cc gnd v fb2 v bias tg1 boost1 sw1 bg1 sense1 + 820pf sense1 ? v fb1 extv cc v out 12v 8a* v in 8v to 38v down to 2.2v after 6.8nf start-up run1 v in run2 i th1 i th2 track/ss1 ss2 freq pllin/mode 1.86k ilim drvuv drvset drv cc v mid , 14v** * when v in <8v maximum load current available is reduced **v mid = 14v when v in < 14v v mid follows v in when vin > 14v ltc7813 vprg2 4.7f m top1 , m top2 , m bot1 , m bot2 : infineon bsc027n04ls l1: wrth 7443320100 l2: wrth 7443320470 c in1 , cmid5: kemet t521x336m050ate075 c out3 : kemet t521v476m020ate055 7813 f12 r b1 499k r a1 35.7k
38 for more information www.linear.com/ltc7813 typical a pplica t ions figure 13. wide input range to 5v/8a low i q cascaded boost+buck regulator (v mid boosted to 10v) ltc 7813 7813f 37.4k 1000pf l2 15h l1 3.3h mbot2 mtop2 cmid1,2,3,4,5,6 2.2f cmid7 33f 0.1f mtop1 mbot1 r sense1 6m r sense2 3m c b1 0.1f c b2 0.1f c in1,2 33f c in3,4 2.2f c out1,2 47f c out3 220f 100pf sense2 + sense2 ? bg2 sw2 boost2 tg2 intv cc gnd v fb2 v bias 2.2nf tg1 boost1 sw1 bg1 sense1 + sense1 ? v fb1 extv cc v out 5v 12.7k 8a v in 8v to 60v down to 2.2v after start-up run1 v in run2 i th1 820pf i th2 track/ss1 ss2 freq pllin/mode ilim drvuv drvset drv cc v mid , 10v* 10nf *v mid = 10v when v in < 10v v mid follows v in when vin > 10v ltc7813 vprg2 mtop1: infineon bsc057n08ns3 mbot1: infineon bsc036ne7ns3 mtop2, mbot2: infineon bsc042ne7ns3 l1: wrth 744325330 l2: wrth 744325120 c in1,2 , cmid7: suncon 63hvp33m 3.6k c out3 : sanyo 6tpb220ml 7813 f13 c ss1 0.1f c ss2 0.1f r b1 357k r a1 68.1k 4.7f
39 for more information www.linear.com/ltc7813 typical a pplica t ions figure 14. high efficiency 12v to 60v v in to 24v/5a and 3.3v/8a dc/dc regulator ltc 7813 7813f c1 1000pf m bot2 m top2 c out4,5,6,7,8,9 2.2f c out10 33f m top1 m bot1 8m c8 0.1f r sense1 r b1 215k r a1 68.1k r b2 232k r a2 12.1k c out1,2 c19 4.7f 47f c out3 220f sense2 ? sense2 ? bg2 sw2 boost2 tg2 intv cc gnd c in1 v fb2 v bias tg1 boost1 sw1 bg1 extv cc sense1 + sense1 ? 33f v fb1 v out1 3.3v 8a v in 12v to 60v run1 v in run2 c in2,3,4 i th1 i th2 track/ss1 ss2 freq pllin/mode ilim drvuv drvset drv cc 2.2f *v out2 = 24v when v in < 24v v out2 follows v in when v in > 24v ltc7813 vprg2 v out2 24v* 5a m top1 : infineon bsc057n08ns3 m bot1 : infineon bsc036ne7ns3 m top2 , m bot2 : infineon bsc042ne7ns3 6m l1: wrth 744325240 l2: wrth 7443551370 c in1 , c out1 0: suncon 63hvp33m c out3 : sanyo 6tpb220ml c ss2 0.1f c ss1 0.1f c15 220pf c14 1500pf c13 100pf c16 4.7nf r sense2 r7 4.3k r6 10k c b2 0.1f l2 15h l1 22h c b1 0.1f 7813 f14
40 for more information www.linear.com/ltc7813 typical a pplica t ions figure 15. wide input range to 24v/5a low i q cascaded boost + buck regulator (v mid = 28v) ltc 7813 7813f 37.4k c in1 33f c in2,3,4 4.7f r sense2 6m r sense1 8m 1000pf l2 15h l1 22h mbot2 mtop2 0.1f mtop1 mbot1 c b1 0.1f r b2 332k r a2 14.7k r b1 332k r a1 11.5k c out1 10f 33pf c out2,3 68f 68pf c ss2 0.1f c ss1 0.22f 90.9k sense2 + sense2 ? bg2 sw2 boost2 tg2 intv cc 4.7nf gnd v fb2 v bias tg1 boost1 sw1 bg1 sense1 + sense1 ? v fb1 26.1k v out 24v 5a* v in 4v to 56v down to 2.2v after start-up run1 v in 820pf run2 i th1 i th2 track/ss1 ss2 freq pllin/mode ilim drvuv drvset 27nf drv cc v mid , 28v** * when v in <12v maximum load current available is reduced **v mid = 28v when v in < 28v v mid follows v in when v in > 28v ltc7813 vprg2 mtop1: infineon bsc123n08ns3 mbot1: infineon bsc042ne7ns3 mtop2: infineon bsc026n08ns3 3.6k mbot2: infineon bsc072n08ns3 l1: coilcraft ser1390-473 l2: coilcraft xal1510-153 c in1 , cmid4,5: suncon 63hvh33m c out2,3 : suncon 35ce68lx 7813 f15 c b2 0.1f c mid1,2,3 4.7f c mid4,5 33f 4.7f
41 for more information www.linear.com/ltc7813 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . p ackage descrip t ion uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) please refer to http://www .linear.com/product/ltc7813#packaging for the most recent package drawings. 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) ltc 7813 7813f
42 for more information www.linear.com/ltc7813 ? linear technology corporation 2016 lt 0316 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc7813 r ela t e d p ar t s typical a pplica t ion part number description comments ltc7812 38v synchronous boost+buck controller with low emi and low input/output ripple 4.5v (down to 2.5v after start-up) v in 38v, boost v out up to 60v, 0.8v buck v out 24v, i q = 33a, 5mm 5mm qfn-32 lt m ? 4609 36v in , 34v out , buck-boost module regulator 4.5v v in 36v, 0.8v v out 34v, up to 4a 15mm 15mm lga and bga packages LTM8056 58v in , 48v out , buck-boost module regulator 5v v in 58v, 1.2v v out 48v, up to 5.4a 15mm 15mm 4.92mm bga package ltc3789 high efficiency (up to 98%) synchronous 4-switch buck-boost dc/dc controller 4 v v in 38v, 0.8v v out 38v, ssop-28, 4mm 5mm qfn-28 lt ? 3790 60v 4-switch synchronous buck-boost controller 4.7v v in 60v, 1.2v v out 60v, tssop-38 lt8705 80v v in and v out synchronous 4-switch buck-boost dc/dc controller 2.8 v v in 80v, 1.3v v out 80v, regulates v out , i out , v in , i in , 5mm 7mm qfn-38, modified tssop package for high voltage ltc 3769 low i q , 60v synchronous step-up dc/dc controller 4.5v (down to 2.3v after start-up) v in 60v, v out up to 60v, i q = 28a pll fixed frequency 50khz to 900khz, 4mm 4mm qfn-24, tssop-20e ltc3891 low i q , 60v synchronous step-down controller with 99% duty cycle pll fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3859al 38v low i q triple output, buck/buck/boost synchronous controller with 28a burst mode i q 4.5v(down to 2.5v after start-up) v in 38v, v out up to 60v, buck v out range: 0.8v to 24v ltc3899 60v, triple output, buck/buck/boost synchronous controller with 29a burst mode i q 4.5v (down to 2.2v after start-up) v in 60v, v out up to 60v, buck v out range: 0.8v to 60v ltc3892/ ltc3892-1/ ltc3892-2 60 v low i q , dual, 2-phase synchronous step-down dc/dc controller with 29a burst mode i q 4.5v v in 60v, 0.8v v out 0.99v in , 5mm 5mm qfn-32, tssop-28 packages * when vin < 12v maximum load current available is reduced ** vmid = 20v when vin < 20v v mid follows v in when v in > 20v v out = 20v when v in < 20v v out = 32v when v in > 32v v out follows v in when v in is 20v to 32v low emi, wide input range pass-through cascaded boost+buck regulator ltc 7813 7813f c in1 47f c in2,3,4 2.2f 1000pf l2 4.7h l1 7.3h mbot2 mtop2 mtop1 mbot1 c out1 6.7f 0.1f c out2,3 56f 1000pf 2.05k 3.01k 3.01k sense2 + sense2 ? bg2 sw2 boost2 100pf tg2 intv cc gnd v fb2 v bias tg1 boost1 sw1 bg1 sense1 + 2200pf sense1 ? v fb1 v out 20v to 32v 5a* v in 4v to 56v down to 2.2v after start-up 26.1k run1 v in run2 i th1 i th2 track/ss1 ss2 freq pllin/mode ilim 820pf drvuv drvset drv cc v mid , 20v** ltc7813 vprg2 mtop1: infineon bsc123n08ns3 mtop2, mbot1, mbot2: infineon bsc047n08ns3 l1: wrth 7443551470 l2: wrth 7443551730 10nf c in1 , cmid4: suncon 63hvh47m c out3 : suncon 50hvh56m 7813 ta02 r b1 499k c b1 0.1f c b2 0.1f r a1 12.7k r b2 499k r a2 31.6k c mid1,2,3 2.2f 2.94k c mid4 47f c ss1 0.1f c ss2 0.1f 4.7f

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